It is known to provide a data processing apparatus having logic elements which can communicate with each other over a communication path. Communication between the logic elements occurs via transfers which may be issued from one logic element (referred to herein as the initiator logic element) to another logic element (referred to herein as the recipient logic element) via the communication path. Often, the data processing apparatus will include multiple logic elements, and individual logic elements may be able to act as initiator logic elements for certain transfers and recipient logic elements for other transfers. In such a data processing apparatus, it is known to provide bus logic for providing the required communication paths between the various logic elements. One example of such bus logic is an interconnect circuit which provides multiple connections over which communication paths can be established between particular initiator logic elements and particular recipient logic elements.
As data processing apparatus increase in complexity, the number of logic elements provided within the data processing apparatus increase, and this increases the complexity of the bus logic. Typically bus logic may provide a larger number of paths for routing transfers between the various logic elements connected to the bus logic, and due to the general desire to keep such data processing apparatus as small as possible, the physical conductors laid out within the data processing apparatus to form these paths are becoming thinner and thinner. Typically the paths are formed from a metal such as copper, and in recent designs the individual conductive lines are getting so thin that resistance along those lines is becoming problematic. In particular, as the resistance and capacitance increases, the time taken for signals to propagate along the paths increases, reducing the performance of the data processing apparatus.
With the aim of seeking to combat this problem, it is known to provide buffer circuits within individual communication paths which are used to assist in speeding the propagation of the signals along the communication path. In particular, by the use of such buffer circuits, individual communication paths are broken down into smaller sections and the buffer circuits are used to amplify the signals as they are propagated from one section to another along the communication path. As a result, this improves the speed of propagation of signals along the communication path.
However, the introduction of such buffer circuits introduces a new problem, namely an increase in power consumption due to leakage currents within the buffer circuits, most notably substrate and gate leakage currents within the individual transistors forming the buffer circuits. In some implementations, power consumption is a very important issue, and in such implementations it is clearly desirable to seek to reduce the effects of such leakage current.
A number of known techniques have been developed for seeking to reduce such leakage current. For example, the article “Leakage-Aware Interconnect for On-Chip Network” by Yuh-Fang Tsai et al, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (Date 2005), pages 230 to 231, describes a number of leakage-aware interconnect designs where a mixture of high threshold voltage and nominal threshold voltage transistors are used to form the buffers, this giving rise to a buffer design that has less leakage current. To further reduce leakage current this article describes the use of a special sleep signal which in a standby mode pulls the input to a buffer circuit down to a low voltage level, which is found to further reduce leakage current.
The article “A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters” by Saumil Shah et al, ICCD 2004, pages 138 to 143, also describes the use of mixed threshold voltage transistors to reduce leakage power consumption in buffers (referred to as “repeaters” in that article).
The article “Low-Leakage Repeaters for NoC Interconnects” by Arkadiy Morgenshtein et al, ISCAS 2005, describes several leakage reduction techniques for buffer circuits for Network-on-Chip (NoC) interconnects. Again, mixed threshold voltage designs are described where some of the transistors in the buffer have a low threshold voltage and some have a high threshold voltage. A design described employs header and footer sleep transistors associated with each buffer circuit (or alternates between header sleep transistors and footer sleep transistors from one buffer circuit to the next), which are driven by a clock signal to enable individual buffer circuits to be turned on or off, thereby reducing leakage current.
Whilst such an approach can produce power consumption savings in certain types of systems, for example systems where components are laid out in a regular and structured manner with the clock signal paths being laid out in close proximity to the payload data paths, the effectiveness of the approach is ultimately limited by the distribution of the clock signal, and by the granularity with which the clock signal can be gated for particular blocks of the system. For example, the buffer circuits do not actually retain state and accordingly do not need to be clocked. As a result, in many systems it is highly likely that a suitable clock signal will not be provided in physical proximity to the buffer circuits, and significant adaptation to the layout design would be required to facilitate the routing of a clock signal to those buffer circuits. In addition, if the clock signal were to be used to turn the buffer circuits on and off, then typically additional clock buffering would be required. Further, any individual clock signal will typically be used to control a particular block of components within the system and accordingly it would not be possible to use that clock signal to control only a particular communication path within the system. Accordingly, only a relatively coarse granularity of control can be achieved.
Accordingly, it would be desirable to provide an improved technique for reducing power consumption resulting from leakage current within buffer circuits provided within communication paths of a data processing apparatus.